1. Field
Embodiments discussed herein relate to a semiconductor integrated circuit.
2. Description of Related Art
In a parallel or serial-parallel analog-to-digital (AD) converter, an input analog voltage is applied to a plurality of comparators in which different threshold values are set, and each comparator compares the input analog voltage with the threshold value. Thermometer codes that are output by the plurality of comparators are encoded by an encoder and are converted into binary codes corresponding to a voltage value. For example, a comparison reference voltage corresponding to the threshold value of each of the plurality of comparators may be generated by a resistance ladder.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2003-18008, Japanese Laid-open Patent Publication No. 2002-33663, Japanese Laid-open Patent Publication No. 2008-160593, Non-Patent Document Yasuhiko Fujita, Eiji Masuda, Shigemi Sakamoto, Tatsuo Sakaue, Yasushi Sato; A bulk CMOS 20MS/s7b flash ADC, IEEE International Solid-State Circuits Conference, vol. XXVII, pp. 56-57, February 1984, Non-Patent Document Yuko Tamba, Kazuo Yamakido; A CMOS 6b 500M Sample/s ADC for a harddisk drive read channel, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 324-325, February 1999, Non-Patent Document Sanroku Tsukamoto, Ian Dedic, Toshiaki Endo, Kazu-yoshi Kikuta, Kunihiko Goto, Osamu Kobayashi; A CMOS 6-b, 200M sample/s, 3 V-supply A/D converter for a PRML read channel LSI, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1831-1836, November 1996, or Non-Patent Document Geert Van der Plas, Stefaan Decoutere, Stephane Donnay; A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process, IEEE International Solid-State Circuits Conference, vol. XLIX, pp. 566-567, February 2006, etc.